A Designer s Guide to Built In Self Test

Author: Charles E. Stroud
Publisher: Springer Science & Business Media
ISBN: 0306475049
Format: PDF, Mobi
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A recent technological advance is the art of designing circuits to test themselves, referred to as a Built-In Self-Test. This book is written from a designer's perspective and describes the major BIST approaches that have been proposed and implemented, along with their advantages and limitations.

High Performance Memory Testing

Author: R. Dean Adams
Publisher: Springer Science & Business Media
ISBN: 0306479729
Format: PDF, ePub, Docs
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Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test. High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Embedded Processor Based Self Test

Author: Dimitris Gizopoulos
Publisher: Springer Science & Business Media
ISBN: 1402028016
Format: PDF
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Embedded Processor-Based Self-Test is a guide to self-testing strategies for embedded processors. Embedded processors are regularly used today in most System-on-Chips (SoCs). Testing of microprocessors and embedded processors has always been a challenge because most traditional testing techniques fail when applied to them. This is due to the complex sequential structure of processor architectures, which consists of high performance datapath units and sophisticated control logic for performance optimization. Structured Design-for-Testability (DfT) and hardware-based self-testing techniques, which usually have a non-trivial impact on a circuit’s performance, size and power, can not be applied without serious consideration and careful incorporation into the processor design. Embedded Processor-Based Self-Test shows how the powerful embedded functionality that processors offer can be utilized as a self-testing resource. Through a discussion of different strategies the book emphasizes on the emerging area of Software-Based Self-Testing (SBST). SBST is based on the idea of execution of embedded software programs to perform self-testing of the processor itself and its surrounding blocks in the SoC. SBST is a low-cost strategy in terms of overhead (area, speed, power), development effort and test application cost, as it is applied using low-cost, low-speed test equipment. Embedded Processor-Based Self-Test can be used by designers, DfT engineers, test practitioners, researchers and students working on digital testing, and in particular processor and SoC test. This book sets the framework for comparisons among different SBST methodologies by discussing key requirements. It presents successful applications of SBST to a number of embedded processors of different complexities and instruction set architectures.

Advances in Electronic Testing

Author: Dimitris Gizopoulos
Publisher: Springer Science & Business Media
ISBN: 0387294090
Format: PDF, Mobi
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This is a new type of edited volume in the Frontiers in Electronic Testing book series devoted to recent advances in electronic circuits testing. The book is a comprehensive elaboration on important topics which capture major research and development efforts today. "Hot" topics of current interest to test technology community have been selected, and the authors are key contributors in the corresponding topics.

Power Constrained Testing of VLSI Circuits

Author: Nicola Nicolici
Publisher: Springer Science & Business Media
ISBN: 0306487314
Format: PDF, Kindle
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This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. It surveys existing techniques and presents several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths.

2000 IEEE 1st International Symposium on Quality Electronic Design

Author:
Publisher: IEEE Computer Society Press
ISBN: 9780769505251
Format: PDF, ePub, Docs
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The 48 regular papers and 19 poster papers from the March 2000 symposium report on design techniques, processes, electronic design automation (EDA) tools, and methodologies geared toward improvement in the quality of integrated circuit designs. The regular papers are divided into sections on DSM modeling, emerging process and device technology, quality of design and EDA tools, emerging integrity issues, low power design and test, quality of IP blocks, the impact of emerging processes on design quality, quality definitions and metrics, design for manufacturability, and VDSM capacitive and inductive issues. No subject index.